The present invention relates generally to integrated circuit testing and more specifically to structural testing of integrated circuits.
Integrated circuit test paradigms are defined by (a) the kind of test; (b) the kind of tester that stores and delivers the test; and (c) the test delivery mechanisms. The kind of test can be either structural or functional. Structural tests target manufacturing defects and attempt to ensure the manufacturing correctness of basic devices such as wires, transistors, etc. Functional tests, on the other hand, target device functionality and attempt to ensure that the device is functioning correctly. Functional tests are written primarily for architectural verification and silicon debug. Structural tests, on the other hand, are used primarily for manufacturing testing. Testers come in two varieties: functional and structural. Functional testers can drive a large number of input/output (I/O) pins at high data transfer rates with great timing accuracy. On the other hand, structural testers are limited in the number of I/O pins they can drive, as well as the speed and accuracy with which they can deliver data to the I/O pins. The cost of structural testers is considerably lower than the cost of functional testers. Tests can be delivered in one of two ways. The device""s normal functional channels are used and the device runs at operating speed. Alternatively, special design-for-test (DFT) channels can be designed, and tests are applied through these channels at less than operational speed.
The test paradigm in use by many integrated circuit manufacturers today uses functional testers and functional tests. Unlike other test methods, functional testing does not require the behavior of the device under test (DUT) to be changed during the test mode. Thus, functional testing allows integrated circuit manufacturers to test a very large number of xe2x80x9cactual functional pathsxe2x80x9d at speed using millions of vectors in a very short period of time, to thoroughly test all device I/Os with xe2x80x9ctester-per-pinxe2x80x9d ATE technology, and to test embedded caches in a proper functional mode. These tests are delivered using the functional channels and the functional tests are written manually. Such functional testing is facing serious challenges due to the rising cost of manual test generation and the increasing cost of high-speed testers. Using functional testers requires huge capital investment over short periods of time since they become obsolete very quickly. If current trends continue, the cost of testing a device could constitute a significant portion of the manufacturing cost. Thus, as the complexity of microprocessors increases, manual test writing for future microprocessors and other integrated circuits will become prohibitively expensive as well as time consuming.
As a result, the testing paradigm that is evolving among integrated circuit manufacturers is to use low-cost-low-pin-count structural testers and use automatic test pattern generation (ATPG) tools to generate the required tests. The tests being generated are structural tests. Structural testers have a small set of pins that operate at a lower frequency than the device and contact only a subset of its I/O pins. The device needs to be equipped with special DFT access ports to load and unload the vectors from the tester. The boundary scan test access port, scan input and output pins, and direct access test buses are typically used for this purpose.
Traditional I/O functional testing relies on the ability of the tester to control and observe the data, timing, and levels of each pin of the device under test connected to a tester channel. However, with the increasing use of structural testers, dedicated pin electronics are no longer available on the tester to make testing measurements on each I/O pin on the device.
Currently there is no method that allows structural testing of an I/O logic path at operating speed without being able to access device pins externally. What is needed is a method and apparatus to allow structural testing of the path between the core logic and the I/O logic to the pin level at speed when no external connection can be made to such device pins.